Thin film transistor array panel having double-layered oxide semiconductor structure and method for manufacturing the same

ABSTRACT

A thin film transistor array panel includes: a gate line including a gate electrode; a first gate insulating layer on the gate line; a semiconductor layer on the first gate insulating layer and overlapping the gate electrode; a second gate insulating layer on the semiconductor layer and the first gate insulating layer, and an opening in the second gate insulating layer and through which the semiconductor layer is exposed; drain and source electrodes on the second gate insulating and semiconductor layers and facing each other; a first field generating electrode; and a second field generating electrode connected to the drain electrode. The semiconductor layer includes an oxide semiconductor layer, and first and second auxiliary layers on the oxide semiconductor layer and separated from each other. An edge of the drain and source electrodes is disposed inside an edge of the first and second auxiliary layers, respectively.

This application claims priority to Korean Patent Application No.10-2013-0145937 filed on Nov. 28, 2013, and all the benefits accruingtherefrom under 35 U.S.C. §119, the entire contents of which areincorporated herein by reference.

BACKGROUND

(a) Field

The invention relates to a thin film transistor and a method formanufacturing the same.

(b) Description of the Related Art

A liquid crystal display is one of the flat panel displays which havebeen most widely used. The liquid crystal display includes two sheets ofdisplay panels in which field generating electrodes, such as a pixelelectrode and a common electrode, are disposed and a liquid crystallayer interposed therebetween. The liquid crystal display displays animage by applying a voltage to the field generating electrodes togenerate an electric field in the liquid crystal layer, determining anorientation of liquid crystal molecules of the liquid crystal layerbased on the generated electric field, and controlling a polarization ofincident light.

In the liquid crystal display, each of the two field generatingelectrodes which generate the electric field in the liquid crystal layermay be disposed on a single one of the display panels, such as a thinfilm transistor array panel.

The thin film transistor array panel includes a plurality of thin filmtransistors, in which the thin film transistor is configured of a gateelectrode connected to a gate line, a source electrode connected to adata line, a drain electrode connected to a pixel electrode, asemiconductor layer which is disposed on the gate electrode between thesource electrode and the drain electrode, and the like, and transmits adata signal from a data line to the pixel electrode depending on a gatesignal from the gate line.

A semiconductor is an important factor which determines characteristicsof the thin film transistor. As the semiconductor, amorphous silicon hasbeen mainly used; however, since the amorphous silicon has low chargemobility, there is a limitation in manufacturing a high-performance thinfilm transistor. Further, since the polysilicon has high charge mobilityand the high performance thin film transistor is easily manufactured,but cost is increased and uniformity is reduced, there is a limitationin manufacturing a relatively large thin film transistor array panel.

Therefore, research into a thin film transistor using an oxidesemiconductor which has the electron mobility and an on/off ratio ofcurrent higher than amorphous silicon, is cheaper and has the uniformityhigher than polysilicon, has been conducted.

SUMMARY

One or more exemplary embodiment secures characteristics of a thin filmtransistor, in a thin film transistor array panel including an oxidesemiconductor and two field generating electrodes.

An exemplary embodiment of the invention provides a thin film transistorarray panel, including: an insulating substrate; a gate line on theinsulating substrate and including a gate electrode; a reference voltageline on the insulating substrate, separated from the gate line andincluding an extension; a first gate insulating layer on the insulatingsubstrate, the gate line and the reference voltage line; a semiconductorlayer on the first gate insulating layer and overlapping the gateelectrode; a second gate insulating layer on the semiconductor layer andthe first gate insulating layer, and a semiconductor opening defined inthe second gate insulating layer and through which the semiconductorlayer is exposed; a data line including a source electrode; a drainelectrode on the second gate insulating layer and the semiconductorlayer and facing the source electrode; a first passivation layer on thedata line, the drain electrode and the second gate insulating layer; asecond passivation layer on the first passivation layer; a first fieldgenerating electrode on the second passivation layer; a thirdpassivation layer on the first field generating electrode; a firstcontact hole defined in the first passivation layer, the secondpassivation layer and the third passivation layer and exposing the drainelectrode; and a second field generating electrode on the thirdpassivation layer and connected to the drain electrode through the firstcontact hole. The semiconductor layer includes an oxide semiconductorlayer, and a first auxiliary layer and a second auxiliary layer on theoxide semiconductor layer and separated from each other. An edge of thedrain electrode exposes an edge of the first auxiliary layer, and anedge of the source electrode exposes an edge of the second auxiliarylayer.

The first gate insulating layer, the second gate insulating layer andthe first passivation layer may include silicon oxide.

The first auxiliary layer and the second auxiliary layer may includetitanium, molybdenum or an alloy of titanium-molybdenum.

A second contact hole may be defined in the first gate insulating layer,the second gate insulating layer, the first passivation layer and thesecond passivation layer and through which the extension is exposed.

The first field generating electrode may be connected to the extensionthrough the second contact hole.

The second field generating electrode may include a plurality of branchelectrodes, and horizontal portions connecting the plurality of branchelectrodes to each other.

The second passivation layer may include an organic insulating material.

The thin film transistor array panel may further include a resistanceelectrode including a same material as the data line and in a same layeras the data line.

The resistance electrode may overlap the gate line.

A third contact hole may be defined in the first passivation layer andthe second passivation layer and through which the resistance electrodeis exposed.

The first field generating electrode may be connected to the resistanceelectrode through the third contact hole.

Another exemplary embodiment of the invention provides a method formanufacturing a thin film transistor array panel, including: forming agate line including a gate electrode, and a reference voltage lineseparated from the gate line and including an extension, on aninsulating substrate; forming a first gate insulating layer on theinsulating substrate, the gate line, and the reference voltage line;sequentially forming an oxide semiconductor layer and an auxiliarymaterial layer on, the first gate insulating layer; forming a secondgate insulating layer on the auxiliary material layer and the first gateinsulating layer, and a semiconductor opening defined in the second gateinsulating layer and through which the auxiliary material layer isexposed; forming a data metal layer on the second gate insulating layerand the exposed auxiliary material layer; forming a data line includinga source electrode, a drain electrode facing the source electrode, and aresistance electrode, by etching the data metal layer; forming a firstauxiliary layer and a second auxiliary layer exposing the oxidesemiconductor layer by etching the auxiliary material layer;sequentially forming a first passivation layer and a second passivationlayer on the data line, the drain electrode, the resistance electrodeand the exposed oxide semiconductor layer; forming a first fieldgenerating electrode on the second passivation layer; forming a thirdpassivation layer on the first field generating electrode; and forming asecond field generating electrode connected to the drain electrode onthe third passivation layer. An edge of the drain electrode exposes anedge of the first auxiliary layer, and an edge of the source electrodeexposes an edge of the second auxiliary layer.

The etching the data metal layer may include a wet etch and the etchingthe auxiliary material layer may include a dry etch.

The forming the second field generating electrode may include forming aplurality of branch electrodes, and horizontal portions connecting theplurality of branch electrodes to each other.

According to one or more exemplary embodiment of the invention, thesemiconductor layer is between the first gate insulating layer and thesecond gate insulating layer to reduce the interval between thesemiconductor layer and the gate electrode, thereby improving the chargemobility.

Further, the semiconductor layer has a double-layer structure of theoxide semiconductor layer, and the first and second auxiliary layers onthe oxide semiconductor layer, where the edges of the drain electrodeand the source electrode are each inside the edges of the firstauxiliary layer and the second auxiliary layer, thereby reducing theeffect of the metal of the drain electrode and the source electrode onthe oxide semiconductor layer during the forming of the drain electrodeand the source electrode.

In addition, the resistance electrode includes the same metal as thedata line and the first field generating electrode is connected to theresistance electrode, thereby reducing the electrical resistance of thefirst field generating electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages and features of this disclosure willbecome more apparent by describing in further detail exemplaryembodiments thereof with reference to the accompanying drawings, inwhich:

FIG. 1 is a plan view of an exemplary embodiment of a thin filmtransistor array panel according to the invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panelof FIG. 1 taken along line II-II.

FIG. 3 is a cross-sectional view of the thin film transistor array panelof FIG. 1 taken along line III-III.

FIG. 4 is a cross-sectional view of the thin film transistor array panelof FIG. 1 taken along line IV-IV.

FIG. 5 is a cross-sectional view of the thin film transistor array panelof FIG. 1 taken along line V-V.

FIGS. 6 to 26 are cross-sectional views of an exemplary embodiment of amethod for manufacturing a thin film transistor array panel according tothe invention.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments of the invention will be described indetail with reference to the accompanying drawings. As those skilled inthe art would realize, the described exemplary embodiments may bemodified in various different ways, all without departing from thespirit or scope of the invention. On the contrary, exemplary embodimentsintroduced herein are provided to make disclosed contents thorough andcomplete and sufficiently transfer the spirit of the invention to thoseskilled in the art.

In addition, the size and thickness of each configuration shown in thedrawings are arbitrarily shown for understanding and ease ofdescription, but the invention is not limited thereto.

In the drawings, the thickness of layers, films, panels, regions, etc.,are exaggerated for clarity. In the drawings, for understanding and easeof description, the thickness of some layers and areas is exaggerated.It will be understood that when an element such as a layer, film,region, or substrate is referred to as being “on” another element, itcan be directly on the other element or intervening elements may also bepresent. As used herein, the term “and/or” includes any and allcombinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third,etc., may be used herein to describe various elements, components,regions, layers and/or sections, these elements, components, regions,layers and/or sections should not be limited by these terms. These termsare only used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of the invention.

Spatially relative terms, such as “beneath,” “lower,” “above,” “upper”and the like, may be used herein for ease of description to describe therelationship of one element or feature to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation, in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “beneath” relative toother elements or features would then be oriented “above” relative tothe other elements or features. Thus, the exemplary term “beneath” canencompass both an orientation of above and below. The device may beotherwise oriented (rotated 90 degrees or at other orientations) and thespatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a,” “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. In addition, unless explicitly described to the contrary, theword “comprise” and variations such as “comprises” or “comprising”, willbe understood to imply the inclusion of stated elements but not theexclusion of any other elements.

Further, throughout the specification, a “plane shape” means whenviewing an object portion from the top and a “cross section shape” meanswhen viewing a cross section of an object portion vertically taken alongfrom a side.

“About” or “approximately” as used herein is inclusive of the statedvalue and means within an acceptable range of deviation for theparticular value as determined by one of ordinary skill in the art,considering the measurement in question and the error associated withmeasurement of the particular quantity (i.e., the limitations of themeasurement system). For example, “about” can mean within one or morestandard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

All methods described herein can be performed in a suitable order unlessotherwise indicated herein or otherwise clearly contradicted by context.The use of any and all examples, or exemplary language (e.g., “suchas”), is intended merely to better illustrate the invention and does notpose a limitation on the scope of the invention unless otherwiseclaimed. No language in the specification should be construed asindicating any non-claimed element as essential to the practice of theinvention as used herein.

Hereinafter, the invention will be described in detail with reference tothe accompanying drawings.

An exemplary embodiment of a thin film transistor array panel accordingto the invention will be described with reference to FIGS. 1 to 5.

FIG. 1 is a plan view of an exemplary embodiment of a thin filmtransistor array panel according to the invention, FIG. 2 is across-sectional view of the thin film transistor array panel of FIG. 1taken along line II-II, FIG. 3 is a cross-sectional view of the thinfilm transistor array panel of FIG. 1 taken along line III-III, FIG. 4is a cross-sectional view of the thin film transistor array panel ofFIG. 1 taken along line IV-IV, and FIG. 5 is a cross-sectional view ofthe thin film transistor array panel of FIG. 1 taken along line V-V.

Referring to FIGS. 1 to 5, a plurality of gate lines 121 and a pluralityof reference voltage lines 125 which are separated from each other aredisposed on an insulating substrate 110. The insulating substrate 100may include transparent glass or plastic.

Each gate line 121 transmits gate signals, substantially extendshorizontally in the plan view, and includes a plurality of protrudinggate electrodes 124. Further, each gate line 121 may include a gate padpart (not shown) having a relatively wide plane area for connection withanother layer or an external driving circuit (not shown). The gate line121 includes an upper gate line portion 121 r and a lower gate lineportion 121 p and the gate electrode 124 includes an upper gateelectrode portion 124 r and a lower gate electrode portion 124 p.

Each reference voltage line 125 transmits a predetermined voltage suchas reference voltage, may substantially extend in a horizontal directionin the plan view and may be substantially parallel with the gate line121. Each reference voltage line 125 includes a plurality of extensions126. The reference voltage line 125 includes an upper reference voltageline portion (not illustrated) and a lower reference voltage lineportion (not illustrated) and the extension 126 includes an upperextension portion 126 r and a lower extension portion 126 p.

Herein, the upper gate line portion 121 r, the upper gate electrodeportion 124 r and the upper extension portion 126 r include copper (Cu)and are in a same layer. The lower gate line portion 121 p, the lowergate electrode portion 124 p and the lower extension portion 126 pinclude titanium (Ti) or molybdenum (Mo) and are in a same layer. Across-sectional thickness of the upper gate line portion 121 r, theupper gate electrode portion 124 r and the upper extension portion 126 ris larger than that of the lower gate line portion 121 p, the lower gateelectrode portion 124 p, and the lower extension portion 126 p.

Further, the upper reference voltage line portion includes copper and isin the same layer as the upper gate line portion 121 r, the upper gateelectrode portion 124 r and the upper extension portion 126 r. The lowerreference voltage line portion includes titanium or molybdenum and is inthe same layer as the lower gate line portion 121 p, the lower gateelectrode portion 124 p and the lower extension portion 126 p. Across-sectional thickness of the upper reference voltage line portion islarger than that of the lower reference voltage line portion.

A first gate insulating layer 140 is disposed on the gate line 121 andthe reference voltage line 125. The first gate insulating layer 140 mayinclude silicon oxide (SiO_(x))

A semiconductor layer 154 is disposed at a portion corresponding to thegate electrode 124 and on the first gate insulating layer 140.

The semiconductor layer 154 includes an oxide semiconductor layer 154 p,and a first auxiliary layer 154 r 1 and a second auxiliary layer 154 r 2which are disposed on the oxide semiconductor layer 154 p.

The oxide semiconductor layer 154 p includes an oxide of zinc (Zn),gallium (Ga), tin (Sn) or indium (In), such as at least one of zincoxide (ZnO), indium-gallium-zinc oxide (InGaZnO₄), indium-zinc oxide(Zn—In—O) and zinc-tin oxide (Zn—Sn—O) which are a composite oxidethereof.

The first auxiliary layer 154 r 1 and the second auxiliary layer 154 r 2include titanium, molybdenum or an alloy of titanium-molybdenum and areseparated from each other to be disposed at both edges of the oxidesemiconductor layer 154 p. That is, the first auxiliary layer 154 r 1and the second auxiliary layer 154 r 2 expose a part of the oxidesemiconductor layer 154 p. A cross-sectional thickness of the firstauxiliary layer 154 r 1 and the second auxiliary layer 154 r 2 issmaller than that of the oxide semiconductor layer 154 p.

A second gate insulating layer 142 is disposed on the first gateinsulating layer 140 and the semiconductor layer 154. The second gateinsulating layer 142 includes silicon oxide (SiO_(x)). A semiconductoropening 145 is defined in the second gate insulating layer 142, throughwhich the semiconductor layer 154 is exposed.

That is, the semiconductor layer 154 is disposed between the first gateinsulating layer 140 and the second gate insulating layer 142.Therefore, an interval between the semiconductor layer 154 and the gateelectrode 124 is smaller than that in the related art.

A plurality of data lines 171, a plurality of drain electrodes 175, anda plurality of resistance electrodes 178 are disposed on the second gateinsulating layer 142 and the semiconductor layer 154.

Each data line 171 transfers a data signal and substantially extends ina vertical direction in the plan view to intersect the gate line 121 andthe reference voltage line 125. Each data line 171 includes a pluralityof source electrodes 173 which extends toward the gate electrode 124.Further, each data line 171 may include a data pad part (not shown)having a relatively wide area for connection with another layer or anexternal driving circuit (not shown).

In the plan view, the drain electrode 175 includes a bar-shaped firstend facing the source electrode 173 and a second end opposite the firstend and having a relatively wide planar area, based on the gateelectrode 124.

A portion of the drain electrode 175 is disposed on the first auxiliarylayer 154 r 1 and a portion of the source electrode 173 is disposed onthe second auxiliary layer 154 r 2. An edge of the drain electrode 175is disposed inside an edge of the first auxiliary layer 154 r 1 and anedge of the source electrode 173 is disposed inside an edge of thesecond auxiliary layer 154 r 2. That is, the edges and edge portionadjacent thereto of the first auxiliary layer 154 r 1 and the secondauxiliary layer 154 r 2, are exposed by the inwardly-disposed drainelectrode 175 and source electrode 173, respectively.

Due to a disposition structure of the drain electrode 175 and the sourceelectrode 173 and the first auxiliary layer 154 r 1 and the secondauxiliary layer 154 r 2, the effect of metal of the drain electrode 175and the source electrode 173 on the oxide semiconductor layer 154 p maybe reduced, during manufacturing of the thin film transistor arraypanel.

The resistance electrode 178 overlaps the gate line 121 and extends inthe same direction as the gate line 121.

The data line 171 includes an upper data line portion 171 r and a lowerdata line portion 171 p and the source electrode 173 includes an uppersource electrode portion 173 r and a lower source electrode 173 p. Thedrain electrode 175 includes an upper drain electrode portion 175 r anda lower drain electrode portion 175 p and the resistance electrode 178includes an upper resistance electrode portion 178 r and a lowerresistance electrode portion 178 p.

Herein, the upper data line portion 171 r, the upper source electrodeportion 173 r, the upper drain electrode portion 175 r and the upperresistance electrode portion 178 r include copper and are in a samelayer. The lower data line portion 171 p, the lower source electrodeportion 173 p, the lower drain electrode portion 175 p and the lowerresistance electrode portion 178 p include titanium or molybdenum andare in a same layer. A cross-sectional thickness of the upper data lineportion 171 r, the upper source electrode portion 173 r, the upper drainelectrode portion 175 r and the upper resistance electrode portion 178 ris larger than that of the lower data line portion 171 p, the lowersource electrode portion 173 p, the lower drain electrode portion 175 pand the lower resistance electrode portion 178 p.

In the plan view, the data line 171 is periodically bent and forms anoblique angle with respect to an extending direction of the gate line121. The oblique angle of the data line 171 with respect to theextending direction of the gate line 121 may be equal to or more thanabout 45 degrees (°). However, in another exemplary embodiment of a thinfilm transistor array panel according to the invention, the data line171 may extend straightly in the vertical direction and be substantiallyperpendicular to the extending direction of the gate line 121.

One gate electrode 124, one source electrode 173 and one drain electrode175 form one thin film transistor (“TFT”) along with the semiconductorlayer 154. A channel of the TFT is formed by the semiconductor layer 154exposed between the source electrode 173 and the drain electrode 175.

A first passivation layer 180 x is disposed on the data line 171, thedrain electrode 175, the resistance electrode 178, and the channel ofthe TFT. The first passivation layer 180 x may include silicon oxide(SiO_(x)).

A second passivation layer 180 y is disposed on the first passivationlayer 180 x. The second passivation layer 180 y includes an organicinsulating material and a surface of the second passivation layer 180 ymay be substantially planarized.

Although not illustrated, in another exemplary embodiment of a TFT arraypanel according to the invention, the second passivation layer 180 y maybe a color filter and a layer may be further disposed on the secondpassivation layer 180 y as the color filter. In an exemplary embodiment,for example, the TFT array panel may further include a capping layerwhich is disposed on the color filter to reduce or effectively preventintroduction of a pigment of the color filter into the liquid crystallayer. The capping layer may include an insulating material such assilicon nitride (SiNx).

A first field generating electrode 131 is disposed on the secondpassivation layer 180 y. The first field generating electrode 131 mayinclude a transparent conductive material such as indium tin oxide(“ITO”) and indium zinc oxide (“IZO”). According to the illustratedexemplary embodiment of the invention, the first field generatingelectrode 131 may have a plate shape. As a plate shape, branchelectrodes are not defined therein. A passivation layer opening 138 isdefined in the first field generating electrode 131 at a portioncorresponding to a first contact hole 183.

A third passivation layer 180 z is disposed on the first fieldgenerating electrode 131, and a second field generating electrode 191 isdisposed thereon. The second field generating electrode 191 may includea transparent conductive material such as ITO and IZO.

The second field generating electrode 191 includes a plurality of branchelectrodes 193, which substantially extend in parallel with each otherand are spaced apart from each other, and lower and upper horizontalparts 192 which connect upper and lower ends of the plurality of branchelectrodes 193 to each other. In the plan view, the branch electrode 193of the second field generating electrode 191 may be bent along the dataline 171, so as to be substantially parallel to the data line 171.

However, in another exemplary embodiment of the TFT array panelaccording to the invention, the data line 171 and the branch electrode193 of the second field generating electrode 191 may each extendstraightly.

The first contact hole 183 is defined in each of the first passivationlayer 180 x, the second passivation layer 180 y and the thirdpassivation layer 180 z, through which a part of the drain electrode 175is exposed. The first contact hole 183 includes a first portion 183 awhich is defined in the first passivation layer 180 x, a second portion183 b which is defined in the second passivation layer 180 y, and athird portion 183 c which is defined in the third passivation layer 180z. A sidewall at the first contact hole 183 defined by surfaces of thefirst passivation layer 180 x, the second passivation layer 180 y andthe third passivation layer 180 z may be substantially linear, but theinvention is not limited thereto.

The horizontal portion 192 of the second field generating electrode 191is electrically connected to the drain electrode 175 through the firstcontact hole 183.

A second contact hole 184 is defined in each of the first passivationlayer 180 x, the second passivation layer 180 y, the first gateinsulating layer 140 and the second gate insulating layer 142, throughwhich a part of the extension 126 of the reference voltage line 125 isexposed.

The first field generating electrode 131 is electrically connected tothe extension 126 of the reference voltage line 125 through the secondcontact hole 184.

A third contact hole 185 is defined in each of the first passivationlayer 180 x and the second passivation layer 180 y, through which a partof the resistance electrode 178 is exposed.

The first field generating electrode 131 is electrically connected tothe resistance electrode 178 through the third contact hole 185.

The first field generating electrode 131 is connected to the referencevoltage line 125 through the second contact hole 184 to be applied witha reference voltage from the reference voltage line 125, and the secondfield generating electrode 191 is connected to the drain electrode 175through the first contact hole 183 to be applied with a data voltagefrom the data line 171. Further, the first field generating electrode131 is connected to the resistance electrode 178 through the thirdcontact hole 185 to reduce an electrical resistance of the first fieldgenerating electrode 131.

The first field generating electrode 131 and the second field generatingelectrode 191, which are applied with a common voltage and a datavoltage, respectively, generate an electric field in a liquid crystallayer (not illustrated).

In the illustrated exemplary embodiment of the TFT array panel accordingto the invention, the plate-shaped first field generating electrode 131is disposed beneath the third passivation layer 180 z and the secondfield generating electrode 191 having the plurality of branch electrodes193 is disposed above the third passivation layer 180 z, but theinvention is not limited thereto. In another exemplary embodiment of theTFT array panel according to the invention, the second field generatingelectrode 191 having the plurality of branch electrodes 193 may bedisposed beneath the third passivation layer 180 z and the plate-shapedfirst field generating electrode 131 may be disposed above the thirdpassivation layer 180 z. In still another exemplary embodiment of theTFT array panel according to the invention, the resistance electrode 178connected to the first field generating electrode 131 is omitted.

Further, in exemplary embodiments, any one of the first field generatingelectrode 131 and the second field generating electrode 191 may includethe plurality of branch electrodes, and the other one may have a plateshape absent the plurality of branch electrodes.

Further, any one of the first field generating electrode 131 and thesecond field generating electrode 191 may be applied with the referencevoltage, and the other one may be applied with the data voltage.

That is, all the features of the above-described exemplary embodiment ofa TFT array panel according to the invention may be applied to devicesin which both the common electrode and the pixel electrode, which aretwo field generating electrodes, are disposed in the single TFT arraypanel.

The first gate insulating layer 140 and the second gate insulating layer142 are disposed between the source electrode 173 and the gate electrode124 and between the drain electrode 175 and the gate electrode 124. Thesemiconductor layer 154 is disposed between the first gate insulatinglayer 140 and the second gate insulating layer 142 to reduce theinterval between the semiconductor layer 154 and the gate electrode 124,while maintaining the respective intervals between the source electrode173 and the drain electrode 175, and the gate electrode 124 of therelated art, thereby improving the charge mobility. Therefore, one ormore exemplary embodiment secures the characteristics of the TFT.

Further, the semiconductor layer 154 has a double-layer structureincluding the oxide semiconductor layer 154 p, and the first and secondauxiliary layers 154 r 1 and 154 r 2, where the edges of the drainelectrode 175 and the source electrode 173 are each disposed inside theedges of the first auxiliary layer 154 r 1 and the second auxiliarylayer 154 r 2, thereby reducing the effect of metal of the drainelectrode 175 and the source electrode 173 on the oxide semiconductorlayer 154 p during forming the drain electrode 175 and the sourceelectrode 173 in manufacturing the TFT array panel.

In addition, the resistance electrode 178 including the same metal asthe data line 171 and the first field generating electrode 131 isconnected to the resistance electrode 178, thereby reducing theelectrical resistance of the first field generating electrode 131.

Next, an exemplary embodiment of a method for manufacturing a TFT arraypanel according to the invention will be described with reference toFIGS. 6 to 26 along with FIGS. 2 to 5.

FIGS. 6 to 26 are cross-sectional views of an exemplary embodiment of amethod for manufacturing a TFT array panel according to the invention.

Referring to FIGS. 6 to 9 as views taken along II-II, III-III, IV-IV andV-V of FIG. 1, respectively, a gate line 121 including a gate electrode124 and an extension 126, are formed on an insulating substrate 110, afirst gate insulating layer 140 is formed on the gate line 121 and theextension 126. An oxide semiconductor layer 154 p and an auxiliarymaterial layer 154 r are formed at a part corresponding to the gateelectrode 124, on the first gate insulating layer 140. Further, althoughnot illustrated, at the time of forming the extension 126, a referencevoltage line 125 is also formed.

The gate line 121 includes an upper gate line portion 121 r and a lowergate line portion 121 p and the gate electrode 124 includes an uppergate electrode portion 124 r and a lower gate electrode portion 124 p.The extension 126 includes an upper extension portion 126 r and a lowerextension portion 126 p.

Herein, the upper gate line portion 121 r, the upper gate electrodeportion 124 r and the upper extension portion 126 r include copper (Cu)and are in a same single layer. The lower gate line portion 121 p, thelower gate electrode portion 124 p and the lower extension portion 126 pinclude titanium or molybdenum and are in a same single layer. Thecross-sectional thickness of the upper gate line portion 121 r, theupper gate electrode portion 124 r and the upper extension portion 126 ris larger than that of the lower gate line portion 121 p, the lower gateelectrode portion 124 p, and the lower extension portion 126 p,respectively.

The first gate insulating layer 140 includes of silicon oxide.

The oxide semiconductor layer 154 p includes an oxide zinc, gallium, tinor indium such as at least one of zinc oxide, indium-gallium-zinc oxide,indium-zinc oxide, and zinc-tin oxide which are a composite oxidethereof. The auxiliary material layer 154 r includes titanium,molybdenum, or an alloy of titanium-molybdenum. The cross-sectionalthickness of the oxide semiconductor layer 154 p is larger than that ofthe auxiliary material layer 154 r.

Referring to FIGS. 10 to 13 as views taken along II-II, III-III, IV-IVand V-V of FIG. 1, respectively, a second gate insulating layer 142 isformed on the first gate insulating layer 140 and the auxiliary materiallayer 154 r, by using silicon oxide.

Referring to FIGS. 14 to 17 as views taken along II-II, III-III, IV-IVand V-V of FIG. 1, respectively, after the auxiliary material layer 154r is exposed by the second gate insulating layer 142, a lower data metallayer 170 p and an upper data metal layer 170 r are sequentially formedon the second gate insulating layer 142 and the exposed auxiliary layer154 r.

The lower data metal layer 170 p includes titanium or molybdenum and theupper data metal layer 170 r includes copper. The upper data metal layer170 r is formed to be thicker than the lower data metal layer 170 p.

Referring to FIGS. 18 to 21 as views taken along II-II, III-III, IV-IVand V-V of FIG. 1, respectively, a data line 171 including a sourceelectrode 173, and a resistance electrode 178 are formed by etching theupper data metal layer 170 r and the lower data metal layer 170 p.

The data line 171 includes an upper data line portion 171 r and a lowerdata line portion 171 p and the source electrode 173 includes an uppersource electrode portion 173 r and a lower source electrode portion 173p. The drain electrode 175 includes an upper drain electrode portion 175r and a lower drain electrode portion 175 p and the resistance electrode178 includes an upper resistance electrode portion 178 r and a lowerresistance electrode portion 178 p.

The drain electrode 175 and the source electrode 173 are separated fromeach other, face each other with respect to the gate electrode 124, andexpose the auxiliary material layer 154 r.

The resistance electrode 178 overlaps the gate line 121.

Referring to FIG. 22 as a partial view taken along II-II of FIG. 1, afirst auxiliary layer 154 r 1 and a second auxiliary layer 154 r 2exposing the oxide semiconductor layer 154 p are formed by etching theauxiliary material layer 154 r exposed by the drain electrode 175 andthe source electrode 173. Herein, the first auxiliary layer 154 r 1 andthe second auxiliary layer 154 r 2, and the oxide semiconductor layer154 p collectively form a semiconductor layer 154.

When the lower data metal layer 170 p and the upper data metal layer 170r are etched (refer to FIG. 18), the lower data metal layer 170 p andthe upper data metal layer 170 r undergo a wet etch by using aphotosensitive film pattern (not illustrated) as a mask and the edges ofthe drain electrode 175 and the source electrode 173 are disposed insidethe edges of the photosensitive film pattern. That is, the edges of thedrain electrode 175 and the source electrode 173 are disposed indifferent positions than the edges of the photosensitive film pattern.

Next, referring again to FIG. 22, when the auxiliary layer 154 rundergoes a dry etch by using the same photosensitive film pattern usedin etching the lower data metal layer 170 p and the upper data metallayer 170 r, the edge of the photosensitive film pattern and the edgesof the first auxiliary layer 154 r 1 and the second auxiliary layer 154r 2 are disposed at the same position when viewed from a plane. That is,edges of the drain electrode 175 and the source electrode 173 are offsetfrom the edges of the first auxiliary layer 154 r 1 and the secondauxiliary layer 154 r 2, even though the same photosensitive filmpattern is used to form these elements.

Therefore, the edge of the drain electrode 175 is disposed inside theedge of the first auxiliary layer 154 r 1 and the edge of the sourceelectrode 173 is disposed inside the edge of the second auxiliary layer154 r 2, in the plan view.

Referring to FIGS. 23 to 26 as views taken along II-II, III-III, IV-IVand V-V of FIG. 1, respectively, a first passivation layer 180 x isformed on the data line 171, the drain electrode 175, the resistanceelectrode 178 and the exposed oxide semiconductor layer 154 p by usingsilicon oxide. A second passivation layer 180 y is formed on the firstpassivation layer 180 x by using an organic insulating material.

A first portion 183 a of a first contact hole 183 is formed in the firstpassivation layer 180 x and a second portion 183 b of the first contacthole 183 is formed in the second passivation layer 180 y. The firstportion 183 a and the second portion 183 b expose a part of the drainelectrode 175.

Further, a second contact hole 184 is formed in the first passivationlayer 180 x, the second passivation layer 180 y, the first gateinsulating layer 140 and the second gate insulating layer 142 to exposea part of the extension 126.

Further, a third contact hole 185 is formed in the first passivationlayer 180 x and the second passivation layer 180 y to expose a part ofthe resistance electrode 178.

Next, a first field generating electrode 131 is formed on the secondpassivation layer 180 y. The first field generating electrode 131 isconnected to the extension 126 through the second contact hole 184 andis connected to the resistance electrode 178 through the third contacthole 185.

Further, a passivation layer opening 138 is formed in the first fieldgenerating electrode 131. The passivation layer opening 138 is formed atthe first portion 183 a of the first contact hole 183 and the secondportion 183 b of the first contact hole 183. The passivation layeropening 138 exposes the first portion 183 a of the first contact hole183 and the second portion 183 b of the first contact hole 183.

Referring again to FIGS. 3 to 5, a third passivation layer 180 z isformed on the second passivation layer 180 y. The third passivationlayer 180 z includes a third portion 183 c of the first contact hole183. The third portion 183 c of the first contact hole 183 extends fromthe second portion 183 b of the first contact hole 183.

Next, a second field generating electrode 191 including a plurality ofbranch electrodes 193 and a horizontal portion 192 is formed on thethird passivation layer 180 z. The horizontal portion 192 of the secondfield generating electrode 191 is connected to the drain electrode 175through the first contact hole 183.

While this invention has been described in connection with what ispresently considered to be practical exemplary embodiments, it is to beunderstood that the invention is not limited to the disclosed exemplaryembodiments, but, on the contrary, is intended to cover variousmodifications and equivalent arrangements included within the spirit andscope of the appended claims.

What is claimed is:
 1. A thin film transistor array panel, comprising:an insulating substrate; a gate line on the insulating substrate andcomprising a gate electrode; a reference voltage line on the insulatingsubstrate, separated from the gate line and comprising an extension; afirst gate insulating layer on the insulating substrate, the gate lineand the reference voltage line; a semiconductor layer on the first gateinsulating layer and overlapping the gate electrode; a second gateinsulating layer on the semiconductor layer and the first gateinsulating layer, and a semiconductor opening defined in the second gateinsulating layer and through which the semiconductor layer is exposed; adata line comprising a source electrode; a drain electrode on the secondgate insulating layer and the semiconductor layer, and facing the sourceelectrode; a first passivation layer on the data line, the drainelectrode and the second gate insulating layer; a second passivationlayer on the first passivation layer; a first field generating electrodeon the second passivation layer; a third passivation layer on the firstfield generating electrode; a first contact hole defined in the firstpassivation layer, the second passivation layer and the thirdpassivation layer and exposing the drain electrode; and a second fieldgenerating electrode on the third passivation layer and connected to thedrain electrode through the first contact hole, wherein thesemiconductor layer comprises an oxide semiconductor layer, and a firstauxiliary layer and a second auxiliary layer disposed on the oxidesemiconductor layer and separated from each other, an edge of the drainelectrode exposes an edge of the first auxiliary layer in a plan view,and an edge of the source electrode exposes an edge of the secondauxiliary layer in the plan view.
 2. The thin film transistor arraypanel of claim 1, wherein the first gate insulating layer, the secondgate insulating layer and the first passivation layer comprise siliconoxide.
 3. The thin film transistor array panel of claim 2, wherein thefirst auxiliary layer and the second auxiliary layer comprise titanium,molybdenum or an alloy of titanium-molybdenum.
 4. The thin filmtransistor array panel of claim 3, further comprising a second contacthole defined in the first gate insulating layer, the second gateinsulating layer, the first passivation layer and the second passivationlayer and through which the extension is exposed.
 5. The thin filmtransistor array panel of claim 4, wherein the first field generatingelectrode is connected to the extension through the second contact hole.6. The thin film transistor array panel of claim 5, wherein the secondfield generating electrode comprises a plurality of branch electrodes,and horizontal portions connecting the plurality of branch electrodes toeach other.
 7. The thin film transistor array panel of claim 6, whereinthe second passivation layer comprises an organic insulating material.8. The thin film transistor array panel of claim 1, further comprising aresistance electrode comprising a same material as the data line and ina same layer as the data line.
 9. The thin film transistor array panelof claim 8, wherein the resistance electrode overlaps the gate line. 10.The thin film transistor array panel of claim 9, further comprising athird contact hole defined in the first passivation layer and the secondpassivation layer and through which the resistance electrode is exposed.11. The thin film transistor array panel of claim 10, wherein the firstfield generating electrode is connected to the resistance electrodethrough the third contact hole.
 12. A method for manufacturing a thinfilm transistor array panel, comprising: forming a gate line comprisinga gate electrode, and a reference voltage line separated from the gateline and comprising an extension, on an insulating substrate; forming afirst gate insulating layer on the insulating substrate, the gate line,the gate electrode and the reference voltage line; sequentially formingan oxide semiconductor layer and an auxiliary material layer on the gateelectrode and the first gate insulating layer; forming a second gateinsulating layer on the auxiliary material layer and the first gateinsulating layer, and a semiconductor opening defined in the second gateinsulating layer to expose the auxiliary material layer; forming a datametal layer on the second gate insulating layer and the exposedauxiliary material layer; forming a data line comprising a sourceelectrode, a drain electrode facing the source electrode, and aresistance electrode, by etching the data metal layer; forming a firstauxiliary layer and a second auxiliary layer separated from each otherto expose the oxide semiconductor layer, by etching the auxiliarymaterial layer; sequentially forming a first passivation layer and asecond passivation layer on the data line, the drain electrode, theresistance electrode and the exposed oxide semiconductor layer; forminga first field generating electrode on the second passivation layer;forming a third passivation layer on the first field generatingelectrode; and forming a second field generating electrode on the thirdpassivation layer and connected to the drain electrode, wherein an edgeof the drain electrode exposes an edge of the first auxiliary layer in aplan view, and an edge of the source electrode exposes an edge of thesecond auxiliary layer in the plan view.
 13. The method of claim 12,wherein the first gate insulating layer, the second gate insulatinglayer and the first passivation layer comprise silicon oxide.
 14. Themethod of claim 13, wherein the auxiliary material layer comprisestitanium, molybdenum or an alloy of titanium-molybdenum.
 15. The methodof claim 14, wherein the etching the data metal layer comprises a wetetch, and the etching the auxiliary material layer comprises a dry etch.16. The method of claim 15, further comprising forming a first contacthole in the first passivation layer, the second passivation layer andthe third passivation layer to expose the drain electrode, wherein thefirst field generating electrode is connected to the drain electrodethrough the first contact hole.
 17. The method of claim 16, furthercomprising forming a second contact hole in the first gate insulatinglayer, the second gate insulating layer, the first passivation layer andthe second passivation layer to expose the extension, wherein the firstfield generating electrode is connected to the extension through thesecond contact hole.
 18. The method of claim 17, further comprisingforming a third contact hole in the first passivation layer and thesecond passivation layer to expose the resistance electrode, wherein theresistance electrode overlaps the gate line, and the first fieldgenerating electrode is connected to the resistance electrode throughthe third contact hole.
 19. The method of claim 18, wherein the formingthe second field generating electrode comprises forming a plurality ofbranch electrodes, and horizontal portions connecting the plurality ofbranch electrodes to each other.
 20. The method of claim 19, wherein thesecond passivation layer comprises an organic insulating material.